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MAX 7000-series CPLD with 2500 gates.A
complex programmable logic device (CPLD) is a programmable logic device with complexity between that of Programmable Array Logics and
Field-programmable gate arrays, and architectural features of both. The building block of a CPLD is the
macro cell, which contains logic implementing
disjunctive normal form expressions and more specialized logic operations.
Features in common with
Programmable array logics:
- Non-volatile configuration memory. Unlike many FPGAs, an external configuration read-only memory isn't required, and the CPLD can function immediately on system start-up.
- For many legacy CPLD devices routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.
Features in common with field programmable gate arrays:
- Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
- Some provisions for logic more flexible than disjunctive normal form expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.
The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.
CPLDs were an evolutionary step from even smaller devices that preceded them,
programmable logic arrays (first shipped by
Signetics), and programmable array logics. These in turn were preceded by Logic family products, that offered no programmability and were "programmed" by wiring several standard logic chips together.
As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future.
See also
External links
- How Programmable Logic Works
Some notable CPLD suppliers